1. Field of the Invention
The present invention relates to a memory, and more particularly, it relates to a memory refreshing stored data.
2. Description of the Background Art
A ferroelectric memory (FeRAM: ferroelectric random-access memory) is generally known as an exemplary nonvolatile memory. The ferroelectric memory utilizes pseudo-capacitance change responsive to the direction of polarization of a ferroelectric substance as a memory element. Simple matrix and one-transistor ferroelectric memories causing disturbance of data stored in memory cells are known as such ferroelectric memories. In other words, it is known that each of the simple matrix one-transistor ferroelectric memories causes the so-called disturbance in which data are lost due to reduced quantities of polarization of ferroelectric capacitors resulting from application of a prescribed voltage to memory cells connected to word lines other than a selected word line in a rewrite operation after a read operation and a write operation on memory cells including ferroelectric capacitors. In order to suppress such disturbance, each of the simple matrix and one-transistor ferroelectric memories performs a refresh operation.
In relation to a memory performing a refresh operation, various techniques have been proposed in order to perform the refresh operation uncompetitively with an internal access operation. For example, Japanese Patent Laying-Open No. 2001-229674 discloses a DRAM (dynamic random-access memory) performing an internal access operation (read or write operation) in synchronization with an internal clock having a shorter cycle than an external clock having a prescribed cycle. In general, a DRAM must perform a refresh operation upon a lapse of a constant period. In the DRAM disclosed in Japanese Patent Laying-Open No. 2001-229674, the number of internal clocks generated in a constant period is larger than the number of external clocks input in the constant period since the cycle of the internal clock is shorter than that of the external clock. Therefore, the internal clock is periodically generated also when no external access operation is performed in synchronization with the external clock, to result in periodic generation of an internal clock irrelevant to an internal access operation corresponding to an external access operation. The DRAM disclosed in Japanese Patent Laying-Open No. 2001-229674 is so formed as to perform a refresh operation consisting of a read operation and a rewrite operation in synchronization with this internal clock irrelevant to an internal access operation. Thus, the DRAM can perform the refresh operation without hindering any internal access operation.
However, the conventional DRAM disclosed in Japanese Patent Laying-Open No. 2001-229674 performs the refresh operation by continuously performing the read operation and the rewrite operation in synchronization with the internal clock having the cycle shorter by a prescribed ratio than that of the external clock, and hence the cycle of the internal clock is disadvantageously increased. Thus, the cycle of the external clock longer than that of the internal clock must also be increased, to disadvantageously result in a long period of the external access operation.